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tlc5510, tlc5510a 8-bit high-speed analog-to-digital converters slas095l ? september 1994 ? revised june 2003 1 post office box 655303 ? dallas, texas 75265 features analog input range ? tlc5510 ...2 v full scale ? tlc5510a ...4 v full scale 8-bit resolution integral linearity error 0.75 lsb max (25 c) 1 lsb max (? 20 c to 75 c) differential linearity error 0.5 lsb max (25 c) 0.75 lsb max (? 20 c to 75 c) maximum conversion rate 20 mega-samples per second (msps) max 5-v single-supply operation low power consumption tlc5510 . . . 127.5 mw typ tlc5510a . . . 150 mw typ (includes reference resistor dissipation) tlc5510 is interchangeable with sony cxd1175 applications digital tv medical imaging video conferencing high-speed data conversion qam demodulators description the tlc5510 and tlc5510a are cmos, 8-bit, 20 msps analog-to-digital converters (adcs) that utilize a semiflash architecture. the tlc5510 and tlc5510a operate with a single 5-v supply and typically consume only 130 mw of power. included is an internal sample-and-hold circuit, parallel outputs with high-impedance mode, and internal reference resistors. the semiflash architecture reduces power consumption and die size compared to flash converters. by implementing the conversion in a 2-step process, the number of comparators is significantly reduced. the latency of the data output valid is 2.5 clocks. the tlc5510 uses the three internal reference resistors to create a standard, 2-v, full-scale conversion range using v dda . only external jumpers are required to implement this option and eliminates the need for external reference resistors. the tlc5510a uses only the center internal resistor section with an externally applied 4-v reference such that a 4-v input signal can be used. differential linearity is 0.5 lsb at 25 c and a maximum of 0.75 lsb over the full operating temperature range. typical dynamic specifications include a differential gain of 1% and differential phase of 0.7 degrees. the tlc5510 and tlc5510a are characterized for operation from ?20 c to 75 c. available options package maximum full scale t a tssop (pw) sop (ns) (tape and reel only) maximum full - scale input voltage 20 cto75 c tlc5510ipw tlc5510insle 2 v ? 20 c to 75 c ? TLC5510AINSle 4 v please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. copyright ? 1994 ? 2003, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 oe dgnd d1(lsb) d2 d3 d4 d5 d6 d7 d8(msb) v ddd clk dgnd refb refbs agnd agnd analog in v dda reft refts v dda v dda v ddd pw or ns package ? (top view) ? available in tape and reel only and ordered as the shown in the available options table below.
tlc5510, tlc5510a 8-bit high-speed analog-to-digital converters slas095l ? september 1994 ? revised june 2003 2 post office box 655303 ? dallas, texas 75265 functional block diagram lower sampling comparators (4-bit) lower encoder (4-bit) lower data latch lower sampling comparators (4-bit) lower encoder (4-bit) upper sampling comparators (4-bit) upper encoder (4-bit) upper data latch clock generator oe d1(lsb) d2 d3 d4 d5 d6 d7 d8(msb) clk refb reft refbs agnd agnd analog in v dda refts 270 ? nom 80 ? nom 320 ? nom resistor reference divider schematics of inputs and outputs equivalent of analog input v dda agnd analog in equivalent of each digital input v ddd dgnd oe , clk equivalent of each digital output v ddd dgnd d1 ? d8
tlc5510, tlc5510a 8-bit high-speed analog-to-digital converters slas095l ? september 1994 ? revised june 2003 3 post office box 655303 ? dallas, texas 75265 terminal functions terminal i/o description name no. i/o description agnd 20, 21 analog ground analog in 19 i analog input clk 12 i clock input dgnd 2, 24 digital ground d1 ? d8 3 ? 10 o digital data out. d1 = lsb, d8 = msb oe 1 i output enable. when oe = low, data is enabled. when oe = high, d1 ? d8 is in high-impedance state. v dda 14, 15, 18 analog supply voltage v ddd 11, 13 digital supply voltage refb 23 i reference voltage in bottom refbs 22 reference voltage in bottom. when using the tlc5510 internal voltage divider to generate a nominal 2-v reference, refbs is shorted to refb (see figure 3). when using the tlc5510a, refbs is connected to ground. reft 17 i reference voltage in top refts 16 reference voltage in top. when using the tlc5510 internal voltage divider to generate a nominal 2-v reference, refts is shorted to reft (see figure 3). when using the tlc5510a, refts is connected to v dda . absolute maximum ratings ? supply voltage, v dda , v ddd 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference voltage input range, v reft , v refb agnd to v dda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog input voltage range, v i(anlg) agnd to v dda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital input voltage range, v i(dgtl) dgnd to v ddd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital output voltage range, v o(dgtl) dgnd to v ddd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a ? 20 c to 75 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions min nom max unit v dda ? agnd 4.75 5 5.25 v supply voltage v ddd ? agnd 4.75 5 5.25 v agnd ? dgnd ? 100 0 100 mv reference input voltage (top), v ref(t) ? tlc5510a v refb +2 4 v reference input voltage (bottom), v ref(b) ? tlc5510a 0 v reft ? 4 v analog input voltage range, v i(anlg) v refb v reft v high-level input voltage, v ih 4 v low-level input voltage, v il 1 v pulse duration, clock high, t w(h) (see figure 1) 25 ns pulse duration, clock low, t w(l) (see figure 1) 25 ns ? the reference voltage levels for the tlc5510 are derived through an internal resistor divider between v dda and ground and therefore are not derived from a separate external voltage source (see the electrical characteristics and text). for the 4 v input range of the t lc5510a, the reference voltage is externally applied across the center divider resistor.
tlc5510, tlc5510a 8-bit high-speed analog-to-digital converters slas095l ? september 1994 ? revised june 2003 4 post office box 655303 ? dallas, texas 75265 electrical characteristics at v dd = 5 v, v reft = 2.5 v, v refb = 0.5 v, f (clk) = 20 mhz, t a = 25 c (unless otherwise noted) digital i/o parameter test conditions ? min typ max unit i ih high-level input current v dd = max, v ih = v dd 5 a i il low-level input current v dd = max, v il = 0 5 a i oh high-level output current oe = gnd, v dd = min, v oh = v dd ? 0.5 v ? 1.5 ma i ol low-level output current oe = gnd, v dd = min, v ol = 0.4 v 2.5 ma i ozh high-level high-impedance-state output leakage current oe = v dd , v dd = max v oh = v dd 16 a i ozl low-level high-impedance-state output leakage current oe = v dd , v dd = min v ol = 0 16 a ? conditions marked min or max are as stated in recommended operating conditions. power parameter test conditions ? min typ max unit i dd supply current f (clk) = 20 mhz, national television system committee (ntsc) ramp wave input, reference resistor dissipation is separate 18 27 ma i f reference voltage current tlc5510 v ref = reft ? refb = 2 v 5.2 7.5 10.5 ma i ref reference voltage current tlc5510a v ref = reft ? refb = 4 v 10.4 15 21 ma ? conditions marked min or max are as stated in recommended operating conditions. static performance parameter test conditions ? min typ max unit self-bias (1), at refb short refb to refbs short reft to refts 0.57 0.61 0.65 self-bias (2), reft ? refb short refb to refbs , short reft to refts 1.9 2.02 2.15 v self-bias (3), at reft short refb to agnd, short reft to refts 2.18 2.29 2.4 r ref reference voltage resistor between reft and refb 190 270 350 ? c i analog input capacitance v i(anlg) = 1.5 v + 0.07 v rms 16 pf tlc5510 f (clk) = 20 mhz, t a = 25 c 0.4 0.75 integral nonlinearity (inl) tlc5510 (clk) , v i = 0.5 v to 2.5 v t a = ? 20 c to 75 c 1 integral nonlinearity (inl) tlc5510a f (clk) = 20 mhz, t a = 25 c 0.4 0.75 tlc5510a (clk) , v i = 0 to 4 v t a = ? 20 c to 75 c 1 lsb tlc5510 f (clk) = 20 mhz, t a = 25 c 0.3 0.5 lsb differential nonlinearity (dnl) tlc5510 (clk) , v i = 0.5 v to 2.5 v t a = ? 20 c to 75 c 0.75 differential nonlinearity (dnl) tlc5510a f (clk) = 20 mhz, t a = 25 c 0.3 0.5 tlc5510a (clk) , v i = 0 to 4 v t a = ? 20 c to 75 c 0.75 e zs zero scale error tlc5510 v ref = reft ? refb = 2 v ? 18 ? 43 ? 68 mv e zs zero - scale error tlc5510a v ref = reft ? refb = 4 v ? 36 ? 86 ? 136 mv e fs full-scale error tlc5510 v ref = reft ? refb = 2 v ? 20 0 20 mv e fs full - scale error tlc5510a v ref = reft ? refb = 4 v ? 40 0 40 mv ? conditions marked min or max are as stated in recommended operating conditions.
tlc5510, tlc5510a 8-bit high-speed analog-to-digital converters slas095l ? september 1994 ? revised june 2003 5 post office box 655303 ? dallas, texas 75265 operating characteristics at v dd = 5 v, v reft = 2.5 v, v refb = 0.5 v, f (clk) = 20 mhz, t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit f maximum conversion rate tlc5510 f i = 1 khz ram p v i(anlg) = 0.5 v ? 2.5 v 20 msps f conv maximum conversion rate tlc5510a f i = 1 - khz ramp v i(anlg) = 0 v ? 4 v 20 msps bw analog input bandwidth at ? 1 db 14 mhz t d(d) digital output delay time c l 10 pf (see note 1 and figure 1) 18 30 ns differential gain ntsc 40 institute of radio en g ineers (ire) 1% differential phase g() modulation wave, f conv = 14.3 msps 0.7 degrees t aj aperture jitter time 30 ps t d(s) sampling delay time 4 ns t en enable time, oe to valid data c l = 10 pf 5 ns t dis disable time, oe to high impedance c l = 10 pf 7 ns in p ut tone = 1 mhz t a = 25 c 45 input tone = 1 mhz full range 43 in p ut tone = 3 mhz t a = 25 c 45 s p urious free dynamic range (sfdr) input tone = 3 mhz full range 46 db spurious free dynamic range (sfdr) in p ut tone = 6 mhz t a = 25 c 43 db input tone = 6 mhz full range 42 in p ut tone = 10 mhz t a = 25 c 39 input tone = 10 mhz full range 39 snr signal to noise ratio t a = 25 c 46 db snr signal - to - noise ratio full range 44 db note 1: c l includes probe and jig capacitance. n n+1 n+2 n+3 n+4 n ? 3n ? 2n ? 1nn+1 t d(d) clk (clock) analog in (input signal) d1 ? d8 (output data) t w(h) t w(l) t d(s) figure 1. i/o timing diagram
tlc5510, tlc5510a 8-bit high-speed analog-to-digital converters slas095l ? september 1994 ? revised june 2003 6 post office box 655303 ? dallas, texas 75265 principles of operation functional description the tlc5510 and tlc5510a are semiflash adcs featuring two lower comparator blocks of four bits each. as shown in figure 2, input voltage v i (1) is sampled with the falling edge of clk1 to the upper comparators block and the lower comparators block(a), s(1). the upper comparators block finalizes the upper data ud(1) with the rising edge of clk2, and simultaneously, the lower reference voltage generates the voltage rv(1) corresponding to the upper data. the lower comparators block (a) finalizes the lower data ld(1) with the rising edge of clk3. ud(1) and ld(1) are combined and output as out(1) with the rising edge of clk4. as shown in figure 2, the output data is delayed 2.5 clocks from the analog input voltage sampling point. input voltage v i (2) is sampled with the falling edge of clk2. ud(2) is finalized with the rising edge of clk3, and ld(2) is finalized with the rising edge of clk4 at the lower comparators block(b). out(2) data appears with the rising edge of clk5. v i (1) v i (2) v i (3) v i (4) clk1 clk2 clk3 clk4 s(1) c(1) s(2) c(2) s(3) c(3) s(4) c(4) s(1) h(1) c(1) s(3) h(3) c(3) h(0) c(0) s(2) h(2) c(2) s(4) h(4) ld( ? 2) out( ? 2) out( ? 1) out(0) out(1) analog in (sampling points) clk (clock) upper comparators block upper data lower reference voltage lower comparators block (a) lower data (a) lower comparators block (b) lower data (b) d1 ? d8 (data output) ud(0) rv(0) ud(1) rv(1) ud(2) rv(2) ud(3) rv(3) ld( ? 1) ld(0) ld(1) ld(2) clk5 figure 2. internal functional timing diagram
tlc5510, tlc5510a 8-bit high-speed analog-to-digital converters slas095l ? september 1994 ? revised june 2003 7 post office box 655303 ? dallas, texas 75265 principles of operation internal referencing tlc5510 the three internal resistors shown with v dda can generate a 2-v reference voltage. these resistors are brought out on v dda , refts, reft, refb, refbs, and agnd. to use the internally generated reference voltage, terminal connections should be made as shown in figure 3. this connection provides the standard video 2-v reference for the nominal digital output. r1 320 ? nom r ref 270 ? nom r2 80 ? nom v dda (analog supply) refts reft refb refbs agnd tlc5510 16 17 22 21 23 18 figure 3. external connections for a 2-v analog input span using the internal-reference resistor divider tlc5510a for an analog input span of 4 v, 4 v is supplied to reft, and refb is grounded and terminal connections should be made as shown in figure 4. this connection provides the 4-v reference for the nominal zero to full-scale digital output with a 4 v pp analog input at analog in. r1 320 ? nom r ref 270 ? nom r2 80 ? nom refts reft refb refbs agnd tlc5510a 16 17 22 21 23 18 4 v v dda (analog supply) figure 4. external connections for 4-v analog input span
tlc5510, tlc5510a 8-bit high-speed analog-to-digital converters slas095l ? september 1994 ? revised june 2003 8 post office box 655303 ? dallas, texas 75265 principles of operation functional operation the output code change with input voltage is shown in table 1. table 1. functional operation input signal step digital output code input signal voltage step msb lsb v ref(b) 255 0 0 0 0 0 0 0 0 ? ? ? ??????? ? ? ? ??????? ? 128 0 1111111 ? 127 1 0000000 ? ? ? ??????? ? ? ? ??????? v ref(t) 0 1 1 1 1 1 1 1 1 application information the following notes are design recommendations that should be used with the device. external analog and digital circuitry should be physically separated and shielded as much as possible to reduce system noise. rf breadboarding or printed-circuit-board (pcb) techniques should be used throughout the evaluation and production process. breadboards should be copper clad for bench evaluation. since agnd and dgnd are connected internally, the ground lead in must be kept as noise free as possible. a good method to use is twisted-pair cables for the supply lines to minimize noise pickup. an analog and digital ground plane should be used on pcb layouts when additional logic devices are used. the agnd and dgnd terminals of the device should be tied to the analog ground plane. v dda to agnd and v ddd to dgnd should be decoupled with 1- f and 0.01- f capacitors, respectively, and placed as close as possible to the affected device terminals. a ceramic-chip capacitor is recommended for the 0.01- f capacitor. care should be exercised to ensure a solid noise-free ground connection for the analog and digital ground terminals. v dda , agnd, and analog in should be shielded from the higher frequency terminals, clk and d0 ? d7. when possible, agnd traces should be placed on both sides of the analog in traces on the pcb for shielding. in testing or application of the device, the resistance of the driving source connected to the analog input should be 10 ? or less within the analog frequency range of interest.
tlc5510, tlc5510a 8-bit high-speed analog-to-digital converters slas095l ? september 1994 ? revised june 2003 9 post office box 655303 ? dallas, texas 75265 application information c1 d1 c3 c4 c5 c6 c2 c11 c9 c7 c8 c10 c12 r5 r4 r2 r1 q1 d3 d2 tp3 r3 c11 fb2 fb3 fb7 fb1 v ref adj tp1 j1 v ddd v dda v dda refts reft v dda analog in agnd agnd refbs refb dgnd 12 11 10 9 8 7 6 5 4 3 2 1 13 14 15 16 17 18 19 20 21 22 23 24 clk v ddd d8 (msb) d7 d6 d5 d4 d3 d2 d1 (lsb) dgnd oe tlc5510 av dd 5 v clock output enable dv dd 5 v video input jp2 jp1 jp4 jp3 ? 5 v note a: shorting jp1 and jp3 allows adjustment of the reference voltage by r5 using temperature-compensating diodes d2 and d3 which compensate for d1 and q1 variations. by shorting jp2 and jp4, the internal divider generates a nominal 2-v reference. location description c1, c3 ? c4, c6 ? c12 0.1- f capacitor c2 10-pf capacitor c5 47- f capacitor fb1, fb2, fb3, fb7 ferrite bead q1 2n3414 or equivalent r1, r3 75- ? resistor r2 500- ? resistor r4 10-k ? resistor, clamp voltage adjust r5 300- ? resistor, reference-voltage fine adjust figure 5. tlc5510 evaluation and test schematic
tlc5510, tlc5510a 8-bit high-speed analog-to-digital converters slas095l ? september 1994 ? revised june 2003 10 post office box 655303 ? dallas, texas 75265 application information c1 d1 c3 c5 c6 c2 c11 c9 c7 c8 c4 r5 r4 r2 r1 q1 r3 c11 fb2 fb3 fb7 fb1 v ref adj tp1 j1 v ddd v dda v dda refts reft v dda analog in agnd agnd refbs refb dgnd 12 11 10 9 8 7 6 5 4 3 2 1 13 14 15 16 17 18 19 20 21 22 23 24 clk v ddd d8 (msb) d7 d6 d5 d4 d3 d2 d1 (lsb) dgnd oe tlc5510a av dd 5 v clock output enable dv dd 5 v video input ? 5 v note a: r5 allows adjustment of the reference voltage to 4 v. r4 adjusts for the desired q1 quiescent operating point. location description c1, c3 ? c4, c6 ? c11 0.1- f capacitor c2 10-pf capacitor c5 47- f capacitor fb1, fb2, fb3, fb7 ferrite bead q1 2n3414 or equivalent r1, r3 75- ? resistor r2 500- ? resistor r4 10-k ? resistor, clamp voltage adjust r5 300- ? resistor, reference-voltage fine adjust figure 6. tlc5510a evaluation and test schematic
tlc5510, tlc5510a 8-bit high-speed analog-to-digital converters slas095l ? september 1994 ? revised june 2003 11 post office box 655303 ? dallas, texas 75265 application information clock clock analog in oe d1 d2 d3 d4 d5 d6 d7 d8 to processor 100 pf 49.9 ? 0.1 f 4.7 f 0.1 f + 4.7 f + 0.1 f 4.7 f + fb1 ? fb3 _ + 0.1 f + 4.7 f av ss 0.1 f 4.7 f + 1 k ? av dd 10 k ? pot 1 k ? 4.7 f 49.9 ? v dda v dda v dda refts reft + 4.7 f 0.1 f 4.7 f + refbs refb 0.1 f 4.7 f + agnd agnd 681 ? v ddd v ddd dgnd dgnd 0.1 f 0.1 f 4.7 f dv dd tlc5510 ths3001 681 ? 5 v ? 5v ? fb ? ferrite bead 5 v figure 7. tlc5510 application schematic
tlc5510, tlc5510a 8-bit high-speed analog-to-digital converters slas095l ? september 1994 ? revised june 2003 12 post office box 655303 ? dallas, texas 75265 application information 50 ? av dd 0.1 f 402 ? 49.9 ? opa690 59 ? 698 ? 698 ? + 6.8 f 0.1 f 100pf 4.7 f 0.1 f 4.7 f 0.1 f 4.7 f 0.1 f 0.1 f 4.7 f 4.7 f 4.7 f 0.1 f 4.7 f 0.1 f +5v dv dd +5v tlc5510a clock clock analog in v dda v dda v dda refts reft refbs refb agnd agnd oe d1 d2 d3 d4 to processor d5 d6 d7 d8 v ddd v ddd dgnd dgnd fb1 ? fb3 v ref 4v + ++ + ? fb ? ferrite bead 402 ? figure 8. tlc5510a application schematic
package option addendum www.ti.com 29-sep-2011 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) TLC5510AINS active so ns 24 34 green (rohs & no sb/br) cu nipdau level-1-260c-unlim TLC5510AINSg4 active so ns 24 34 green (rohs & no sb/br) cu nipdau level-1-260c-unlim TLC5510AINSle obsolete so ns 24 tbd call ti call ti TLC5510AINSr active so ns 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim TLC5510AINSrg4 active so ns 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim tlc5510ins active so ns 24 34 green (rohs & no sb/br) cu nipdau level-1-260c-unlim tlc5510insg4 active so ns 24 34 green (rohs & no sb/br) cu nipdau level-1-260c-unlim tlc5510insle obsolete so ns 24 tbd call ti call ti tlc5510insr active so ns 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim tlc5510insrg4 active so ns 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim tlc5510ipw active tssop pw 24 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlc5510ipwg4 active tssop pw 24 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlc5510ipwr active tssop pw 24 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlc5510ipwrg4 active tssop pw 24 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device.
package option addendum www.ti.com 29-sep-2011 addendum-page 2 (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TLC5510AINSr so ns 24 2000 330.0 24.4 8.2 15.4 2.5 12.0 24.0 q1 tlc5510insr so ns 24 2000 330.0 24.4 8.2 15.4 2.5 12.0 24.0 q1 tlc5510ipwr tssop pw 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 q1 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TLC5510AINSr so ns 24 2000 367.0 367.0 45.0 tlc5510insr so ns 24 2000 367.0 367.0 45.0 tlc5510ipwr tssop pw 24 2000 367.0 367.0 38.0 package materials information www.ti.com 14-jul-2012 pack materials-page 2

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